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d a t a sh eet product speci?cation supersedes data of april 1993 file under integrated circuits, ic02 1996 aug 26 integrated circuits tda8703 8-bit high-speed analog-to-digital converter
1996 aug 26 2 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 features 8-bit resolution sampling rate up to 40 mhz high signal-to-noise ratio over a large analog input frequency range (7.1 effective bits at 4.43 mhz full-scale input) binary or two's complement 3-state ttl outputs overflow/underflow 3-state ttl output ttl compatible digital inputs low-level ac clock input signal allowed internal reference voltage generator power dissipation only 290 mw (typical) low analog input capacitance, no buffer amplifier required no sample-and-hold circuit required. applications general purpose high-speed analog-to-digital conversion digital tv, idtv subscriber tv decoder satellite tv decoders digital vcr. general description the tda8703 is an 8-bit high-speed analog-to-digital converter (adc) for video and other applications. it converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 40 mhz. all digital inputs and outputs are ttl compatible, although a low-level ac clock input signal is allowed. ordering information type number package name description version tda8703 dip24 plastic dual in-line package; 24 leads (600 mil) sot101-1 TDA8703T so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1996 aug 26 3 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 quick reference data notes 1. full-scale sinewave (f i = 4.4 mhz; f clk ; f clk = 27 mhz). 2. the - 3 db bandwidth is determined by the 3 db reduction in the reconstructed output (full-scale signal at input). 3. the circuit has two clock inputs clk and clk. there are four modes of operation: a) ttl (mode 1); clk decoupled to dgnd by a capacitor. clk input is ttl threshold voltage of 1.5 v and sampling on the low-to-high transition of the input clock signal. b) ttl (mode 2); clk decoupled to dgnd by a capacitor. clk input is ttl threshold voltage of 1.5 v and sampling on the high-to-low transition of the input clock signal. c) ac drive modes (modes 3 and 4); when driving the clk input directly and with any ac signal of 0.5 v (peak-to-peak value) imposed on a dc level of 1.5 v, sampling takes place on the low-to-high transition of the clock signal. when driving the clk input with such a signal, sampling takes place on the high-to-low transition. d) if one of the clock inputs is not driven, then it is recommended to decouple this input to dgnd with a 100 nf capacitor. symbol parameter conditions min. typ. max. unit v cca analog supply voltage 4.5 5.0 5.5 v v ccd digital supply voltage 4.5 5.0 5.5 v v cco output stages supply voltage 4.2 5.0 5.5 v i cca analog supply current - 28 36 ma i ccd digital supply current - 19 25 ma i cco output stages supply current - 11 14 ma ile dc integral linearity error -- 1 lsb dle dc differential linearity error -- 1/2 lsb aile ac integral linearity error note 1 -- 2 lsb b - 3 db bandwidth note 2; f clk = 40 mhz - 19.5 - mhz f clk /f clk maximum conversion rate note 3 40 -- mhz p tot total power dissipation - 290 415 mw
1996 aug 26 4 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 block diagram fig.1 block diagram. handbook, full pagewidth 4 8 9 vi v rb v rt 19 18 17 16 clk clk v ccd 7 v cca 23 15 13 24 d2 d3 d4 d5 d6 1 2 12 d1 d0 d7 ttl outputs clock driver tda8703 TDA8703T analog voltage input clock inputs overflow / underflow output data outputs lsb msb 14 analog - to - digital converter latches mga015 20 dgnd 3 agnd analog ground digital ground 11 21 22 tc ce stabilizer ttl output overflow / underflow latch v cco 5 dec
1996 aug 26 5 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 pinning symbol pin description d1 1 data output; bit 1 d0 2 data output; bit 0 (lsb) agnd 3 analog ground v rb 4 reference voltage bottom (decoupling) dec 5 decoupling input (internal stabilization loop decoupling) n.c. 6 not connected v cca 7 positive supply voltage for analog circuits (+5 v) vi 8 analog voltage input v rt 9 reference voltage top (decoupling) n.c. 10 not connected o/uf 11 over?ow/under?ow data output d7 12 data output; bit 7 (msb) d6 13 data output; bit 6 d5 14 data output; bit 5 d4 15 data output; bit 4 clk 16 clock input clk 17 complementary clock input v ccd 18 positive supply voltage for digital circuits (+5 v) v cco 19 positive supply voltage for output stages (+5 v) dgnd 20 digital ground tc 21 input for two's complement output (ttl level input, active low) ce 22 chip enable input (ttl level input, active low) d3 23 data output; bit 3 d2 24 data output; bit 2 fig.2 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 tda8703/ TDA8703T mlb034 d1 d0 agnd v rb dec n.c. v cca vi v rt n.c. o/uf d7 d6 d5 d4 clk v ccd v cco dgnd d3 d2 ce tc clk
1996 aug 26 6 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. the circuit has two clock inputs clk and clk. there are four modes of operation: a) ttl (mode 1); clk decoupled to dgnd by a capacitor. clk input is ttl threshold voltage of 1.5 v and sampling on the low-to-high transition of the input clock signal. b) ttl (mode 2); clk decoupled to dgnd by a capacitor. clk input is ttl threshold voltage of 1.5 v and sampling on the high-to-low transition of the input clock signal. c) ac drive modes (modes 3 and 4); when driving the clk input directly and with any ac signal of 0.5 v (peak-to-peak value) imposed on a dc level of 1.5 v, sampling takes place on the low-to-high transition of the clock signal. when driving the clk input with such a signal, sampling takes place on the high-to-low transition. d) if one of the clock inputs is not driven, then it is recommended to decouple this input to dgnd with a 100 nf capacitor. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal resistance symbol parameter conditions min. max. unit v cca analog supply voltage - 0.3 +7.0 v v ccd digital supply voltage - 0.3 +7.0 v v cco output stages supply voltage - 0.3 +7.0 v v cca - v ccd supply voltage differences - 1.0 +1.0 v v cco - v ccd supply voltage differences - 1.0 +1.0 v v cca - v cco supply voltage differences - 1.0 +1.0 v v vi input voltage range referenced to agnd - 0.3 +7.0 v v clk /v clk ac input voltage for switching (peak-to-peak value) note 1; referenced to dgnd - 2.0 v i o output current - +10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 +70 c t j junction temperature - +125 c symbol parameter value unit r th j-a from junction to ambient in free air sot101-1 55 k/w sot137-1 75 k/w
1996 aug 26 7 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 characteristics v cca =v 7 - v 3 = 4.5 v to 5.5 v; v ccd =v 18 - v 20 = 4.5 v to 5.5 v; v cco =v 19 - v 20 = 4.5 v to 5.5 v; agnd and dgnd shorted together; v cca - v ccd = - 0.5 v to +0.5 v; v cco - v ccd = - 0.5 v to +0.5 v; v cca - v ccd = - 0.5 v to +0.5 v; t amb =0 c to +70 c; unless otherwise speci?ed (typical values measured at v cca =v ccd =v cco = 5 v and t amb =25 c). symbol parameter conditions min. typ. max. unit supply v cca analog supply voltage 4.5 5.0 5.5 v v ccd digital supply voltage 4.5 5.0 5.5 v v cco output stages supply voltage 4.2 5.0 5.5 v i cca analog supply current - 28 36 ma i ccd digital supply current - 19 25 ma i cco output stage supply current all outputs low - 11 14 ma inputs c lock input clk and clk (note 1; referenced to dgnd) v il low level input voltage 0 - 0.8 v v ih high level input voltage 2.0 - v ccd v i il low level input current v clk /v clk = 0.4 v - 400 --m a i ih high level input current v clk /v clk = 0.4 v -- 100 m a v clk /v clk =v ccd -- 300 m a z i input impedance f clk /f clk =10mhz - 4 - k w c i input capacitance f clk /f clk =10mhz - 4.5 - pf v clk - v clk ac input voltage for switching (peak-to-peak value) note 1; dc level = 1.5 v 0.5 - 2.0 v tc and ce ( referenced to dgnd) v il low level input voltage 0 - 0.8 v v ih high level input voltage 2.0 - v ccd v i il low level input current v il = 0.4 v - 400 --m a i ih high level input current v ih = 2.7 v -- 20 m a vi ( analog input voltage referenced to agnd) v vi(b) input voltage (bottom) 1.33 1.41 1.48 v v vi(0) input voltage output code = 0 1.455 1.55 1.635 v v os(b) offset voltage (bottom) v vi(0) - v vi(b) 0.125 - 0.155 v v vi(t) input voltage (top) 3.2 3.36 3.5 v v vi(255) input voltage output code = 255 3.115 3.26 3.385 v v os(t) offset voltage (top) v vi(t) - v vi(255) 0.085 - 0.115 v v vi(p-p) input voltage amplitude (peak-to-peak value) 1.66 1.71 1.75 v i il low level input current v vi = 1.4 v - 0 -m a i ih high level input current v vi = 3.6 v 60 120 180 m a z i input impedance f i = 1 mhz - 10 - k w c i input capacitance f i = 1 mhz - 14 - pf
1996 aug 26 8 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 reference resistance r ref reference resistance v rt to v rb - 220 -w outputs d igital outputs (d7 - d0) ( referenced to dgnd) v ol low level output voltage i o = 1 ma 0 - 0.4 v v oh high level output voltage i o = - 0.4 ma 2.7 - v ccd v i oz output current in 3-state mode 0.4 v < v o < v ccd - 20 - +20 m a switching characteristics (note 2; see fig.3) f clk /f clk maximum clock frequency 40 -- mhz analog signal processing (f clk = 40 mhz) b - 3 db bandwidth note 3 - 19.5 - mhz g d differential gain note 4 - 0.6 - % f d differential phase note 4 - 0.8 - deg f 1 fundamental harmonics (full-scale) f i = 4.43 mhz -- 0db f all harmonics (full-scale), all components f i = 4.43 mhz -- 55 - db svrr1 supply voltage ripple rejection note 5 -- 28 - 25 db svrr2 supply voltage ripple rejection note 5 - 1 2.5 %/v transfer function ile dc integral linearity error -- 1 lsb dle dc differential linearity error -- 1/2 lsb aile ac integral linearity error note 6 -- 2 lsb eb effective bits f i = 4.43 mhz - 7.1 - bits timing (note 7; see figs 3 to 6 ; f clk = 40 mhz) t ds sampling delay -- 2ns t hd output hold time 6 -- ns t dlh output delay time low-to-high transition - 810ns t dhl output delay time high-to-low transition - 16 20 ns t dzh 3-state output delay times enable-to-high - 19 25 ns t dzl 3-state output delay times enable-to-low - 16 20 ns t dhz 3-state output delay times disable-to-high - 14 20 ns t dlz 3-state output delay times disable-to-low - 912ns symbol parameter conditions min. typ. max. unit
1996 aug 26 9 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 notes 1. the circuit has two clock inputs clk and clk. there are four modes of operation: a) ttl (mode 1); clk decoupled to dgnd by a capacitor. clk input is ttl threshold voltage of 1.5 v and sampling on the low-to-high transition of the input clock signal. b) ttl (mode 2); clk decoupled to dgnd by a capacitor. clk input is ttl threshold voltage of 1.5 v and sampling on the high-to-low transition of the input clock signal. c) ac drive modes (modes 3 and 4); when driving the clk input directly and with any ac signal of 0.5 v (peak-to-peak value) imposed on a dc level of 1.5 v, sampling takes place on the low-to-high transition of the clock signal. when driving the clk input with such a signal, sampling takes place on the high-to-low transition. d) if one of the clock inputs is not driven, then it is recommended to decouple this input to dgnd with a 100 nf capacitor. 2. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 2 ns. 3. the - 3 db bandwidth is determined by the 3 db reduction in the reconstructed output (full-scale signal at the input). 4. low frequency ramp signal (v vi(p-p) = 1.8 v and f i = 15 khz) combined with a sinewave input voltage (v vi(p-p) = 0.5 v, f i = 4.43 mhz) at the input. 5. supply voltage ripple rejection: a) svrr1; variation of the input voltage producing output code 127 for supply voltage variation of 1 v: svrr1 = 20 log ( d v vi(127) / d v cca ) b) svrr2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 v: svr2 = { d (v vi(0) - v vi(255) )/(v vi(0) - v vi(255) )} ?d v cca . 6. full-scale sinewave (f i = 4.4 mhz; f clk ; f clk = 27 mhz). 7. output data acquisition: a) output data is available after the maximum delay of t dhl and t dlh .
1996 aug 26 10 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 table 1 output coding and input voltage (referenced to agnd; typical values) table 2 mode selection note 1. x = dont care. binary output bits two's complement output bits step v vi(p-p) o/uf d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 under?ow < 1.55 1 0 000000010000000 0 1.55 0 0 000000010000000 1 - 0 0000000110000001 . . . ................ . . . ................ 254 . 0 1111111001111110 255 3.26 0 1 111111101111111 over?ow >3.26 1 1 111111101111111 tc ce d7-d0 o/uf x (1) 1 high impedance high impedance 0 0 active; twos complement active 1 0 active; binary active fig.3 timing diagram. handbook, full pagewidth t dhl 2.4 v 0.4 v ds t hd t t dlh sample n + 1 1.3 v data n + 1 data n ?1 data n sample n + 2 sample n 1.3 v clk vi d0 - d7 mea105
1996 aug 26 11 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 fig.4 3-state delay timing diagram. handbook, full pagewidth mlb035 - 1 2.4 v 0.4 v reference level (1.4 v) t dhz t dlz t dzh t dzl data outputs ce input fig.5 load circuit for timing measurement; data outputs ( ce = low). handbook, halfpage mgd691 d0 to d7 in916 or in3064 2 k w dgnd v cco 15 pf fig.6 load circuit for timing measurement; 3-state outputs ( ce: f i = 1 mhz; v vi = 3 v); see table 3. handbook, halfpage mbb955 d0 to d7 c5 k w s1 2 k w v cco s2 dgnd in916 or in3064
1996 aug 26 12 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 table 3 mode selection timing measurement switch s1 switch s2 capacitor t dzh open closed 15 pf t dzl closed open 15 pf t dhz closed closed 5 pf t dlz closed closed 5 pf internal pin configurations fig.7 ttl data and overflow/underflow outputs. handbook, halfpage mgd692 dgnd d7 to d0 o/u v cco fig.8 analog inputs. handbook, halfpage mlb037 agnd v cca (x 90) v i fig.9 ce (3-state) input. handbook, halfpage mgd693 dgnd v cco ce fig.10 tc (twos complement) input. handbook, halfpage mlb039 dgnd v ccd tc
1996 aug 26 13 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 fig.11 v rb , v rt and dec. handbook, full pagewidth v rb v rt v cca dec agnd mcd188 fig.12 clk and clk inputs. handbook, full pagewidth 30 k w 30 k w v v ccd clk dgnd mcd189 - 1 ref
1996 aug 26 14 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 application information additional application information will be supplied upon request (please quote number ftv/8901). fig.13 application diagram. handbook, full pagewidth mga014 - 1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 tda8703 TDA8703T d0 d1 d2 d3 d4 d5 d6 dgnd clk agnd dec vi o / uf d7 n.c. clk ce v rb v rt v cca v ccd n.c. v cco tc dgnd agnd 100 pf 47 pf 4.7 m f 22 nf 22 nf 22 nf 5 v 22 w (1) 4.7 m f clk should be decoupled to the dgnd with a 100 nf capacitor, if a ttl signal is used on clk (see chapter characteristics, note 1). clk and clk can be used in a differential mode (see chapter characteristics, note 1). v rb and v rt are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity. if it is required to use the tda8703 in a parallel system configuration, the references (v rb and v rt ) of each tda8703 can be connected together. code 0 will be identical and code 255 will remain in the 1 lsb variation for each tda8703. analog and digital supplies should be separated and decoupled. pins 6 and 10 should be connected to agnd in order to prevent noise influence. (1) it is recommended to decouple v cco through a 22 w resistor especially when the output data of the tda8703 interfaces with a capacitive cmos load device.
1996 aug 26 15 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot101-1 92-11-17 95-01-23 a min. a max. b w m e e 1 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 3.9 3.4 0.25 2.54 15.24 15.80 15.24 17.15 15.90 2.2 5.1 0.51 4.0 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.15 0.13 0.01 0.10 0.60 0.62 0.60 0.68 0.63 0.087 0.20 0.020 0.16 051g02 mo-015ad m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. z max. (1) (1) (1) dip24: plastic dual in-line package; 24 leads (600 mil) sot101-1
1996 aug 26 16 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013ad pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.055 0.42 0.39 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 92-11-17 95-01-24 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1996 aug 26 17 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 aug 26 18 philips semiconductors product speci?cation 8-bit high-speed analog-to-digital converter tda8703 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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